1. Field of the Invention
This invention relates generally to an image processing apparatus and an image processing method and more particularly to an image processing apparatus and an image processing method which can save the memory area and reduce the power consumption and the production cost while maintaining a high access efficiency to a memory for storing data.
2. Description of the Related Art
An existing image transform apparatus which performs transform of an image in a virtual three-dimensional space produces a model of a body shape composed of a combination of polygons such as triangles and performs texture mapping of affixing an image to the model to perform transform of the image. The image transform apparatus is disclosed, for example, in Japanese Patent Laid-Open NO. 2002-83316.
Such an image transform apparatus as described above produces, for texture mapping, a texture address, which represents the position of each pixel of an image after transform to be outputted finally on an image to be affixed in texture mapping, in a unit of a polygon corresponding to the pixel. Then, the texture address is stored for each pixel into a memory.
At this time, the image transform apparatus stores the texture address into an address of the memory corresponding to the position of a pixel corresponding to the texture address on a screen. Accordingly, the texture address produced for each polygon is stored for each pixel into a random address of the memory. In other words, in order to store a texture address, random accessing to the memory is requisite.
Incidentally, as a memory which allows reading out and writing, an SRAM (Static Random Access Memory), an SDRAM (Synchronous Dynamic Random Access Memory) and so forth are available. For example, according to the SDRAM which is more advantageous than the SRAM in terms of the cost, the memory access efficiency is improved by using burst reading/burst writing of data.
Accordingly, where the image transform apparatus uses the SDRAM as a memory for storing texture addresses, in order to perform collective writing of texture addresses, a cache of the write back type is used to perform writing of texture addresses.
In this instance, the cache first reads texture addresses stored already in a plurality of successive addresses of an SDRAM including SDRAM addresses, in which texture addresses to be made an object of writing are stored, in a unit of a cache block (cache line), which is a storage unit of the cache, from the SDRAM.
Then, the texture addresses of an object of writing are overwritten in a region (hereinafter referred to as cache block region) of a cache block size corresponding to the addresses of the SDRAM in which the texture addresses of an object of writing are stored. Then, when eviction of a cache block is to be performed, the cache collectively writes the texture addresses in the overwritten cache block region into addresses of the SDRAM corresponding to the texture addresses.
Then, the cache collectively reads in the texture addresses stored in a plurality of successive addresses of the SDRAM as a cache block in a unit of a cache block from the SDRAM. Then, the texture addresses stored in the random addresses of the SDRAM are updated on the cache. By this, the texture addresses can be written collectively into the SDRAM.